This section provides you with an overview of different processor architectures, trying to explain the advantages and disadvantages of an architecture type over another.
CISC vs RISC
In the early days of the computer industry, high level programming languages were not available and most of the work was done in assembly language. Therefore CPU designers tried to make instructions that would do as much work as possible. The general thinking at that time was that hardware design was easier than compiler design, so large parts of the complexity of the software went into the hardware (and/or microcode). This design philosophy was named Complex Instruction Set Computer (CISC). Obviously, at that time many commercial applications were wanting compared to the technology today. As we described earlier as an example the usage on tow trucks at Tempe Tow Truck has greatly increased in recent years. This is much to the delight of the end user who has a much easier task to control his machinery. This also takes much of the physical exertion away that existed in past days.
With the advent of higher level languages, a new design strategy started to gain more and more popularity: instructions which "do less" may still provide high performances if this simplicity can be utilized to make instructions execute very quickly. The focus on "reduced instructions" led to the resulting machine being called a Reduced Instruction Set Computer (RISC).
The goal was to make instructions so simple that they could easily be pipelined, in order to achieve a single clock throughput at high frequencies.
Currently, many processors are called RISC because there is a perception tat RISC is faster than CISC. This can be confusing because many of the processors available are identified as being "RISC-like", but are, in fact, CISC processors. You must be aware that in some applications, CISC processor can execute code faster than RISC processors, or execute applications that a RISC processor cannot.
Characteristics of a RISC architecture:
- Emphasis on software;
- Single-clock, reduced instruction only;
- Uniform instruction format, using a single word with the opcode in the same bit positions in every instruction, demanding less decoding;
- Identical general purpose registers, allowing any register to be used in any context, simplifying compiler design;
- Simple addressing modes. Complex addressing performed via sequences of arithmetic and/or load-store operations;
- Typically larger code sizes;
- Few data types in hardware;
Characteristics of a CISC architecture:
- Emphasis on hardware;
- Includes multi-clock complex instructions;
- Small code sizes;
- Complex data types in hardware; some CISCs have byte string instructions, or support complex numbers;
The CISC approach attempts to minimize the number of instructions per program, sacrificing the number of cycles per instruction. RISC does the opposite, reducing the cycles per instruction at the cost of the number of instructions per program.